Generally speaking, a parallel bus has multiple data lines and a single clock line. Data is valid—and sampled—on a specified edge (typically rising or falling) of the clock line.
Top Resources
Wikipediaarrow-up-right
Example Simple Parallel Parts
Serial/Parallel Port Adapterarrow-up-right
What Logic Decodes
Rising edge or falling edge of clock
One to eight data lines
Last updated 2 months ago
