Saleae Support
HomeDownloadUser ForumContact Us
  • Saleae Support
  • Orders & Shipping
    • Place an Online Order
    • Place a Purchase Order (PO)
    • Get a Quote
    • Check your Order Status
    • Distributors
    • Pricing and Availability
    • Discounts
    • Tax & VAT Exemption
    • Saleae Business Information
    • Shipping Policy
    • Receiving Invoices
    • Sales FAQ
      • What Is Included with the Product?
      • What Accessories Should I Purchase with My Device?
      • Is the Saleae Software Sold Separately?
      • Does Saleae Have a Trade-In or Upgrade Plan?
      • How Can I Find the Current Status of My Order?
      • Part Numbers, ECCN, HS Codes, and Country of Origin
      • Discontinued Products
      • International Customs and Duty Information
      • Does Saleae Offer Demo Units or Units on Loan?
      • When Is My Card Charged?
      • Unable to Ship to PO Box Error
      • Referred a Friend? Email Us!
      • Does Saleae Provide Drop-Shipping Service?
  • Getting Started
    • Setup
    • Configure
    • Record
    • Navigate
    • Measure
    • Trigger
    • Protocols
  • User Guide
    • Product Summary
    • Safety & Warranty
    • Supported Voltages
    • Device Calibration
    • Using Logic
      • Navigating the Software
      • Connecting the Logic Analyzer
      • Logic Accessories
      • Device Settings
      • Capture Modes
      • Navigating Your Data
      • Time Bar Settings
      • Measurements, Timing Markers & Notes
      • Capture & Preset File Management
      • Exporting Data
      • Delete Part of your Capture
      • Analyzers
      • Data Table & Terminal View
      • Color Themes
      • Demo Mode
      • Software Glitch Filter
      • Keyboard Shortcuts
      • Automatic Updates
      • Message Us Directly
  • Software
    • Supported Operating Systems
    • Download
    • Installation
    • Firmware Updates
    • Driver Install
    • Legacy Software
      • Logic 1.x Download (Deprecated)
      • Logic 1.x Installation (Deprecated)
      • Logic 1.x Changelog (Deprecated)
      • Logic 1.x User Guide (Deprecated)
  • Protocol Analyzers
    • Supported Protocols
    • Analyzer User Guides
      • Async Serial Analyzer - User Guide
        • Decode UART
        • Decode RS-232, RS-485, & RS-422
      • SPI Analyzer - User Guide
      • I2C Analyzer - User Guide
      • CAN Analyzer - User Guide
      • Simple Parallel Analyzer - User Guide
      • I2S / PCM Analyzer - User Guide
      • DMX-512 Analyzer - User Guide
      • SMBus Analyzer - User Guide
      • Decode Differential and High Voltage Data
  • Software Extensions
    • Extension Installation
    • Create and Use Extensions
    • High-Level Analyzer (HLA) Extensions
      • Shared High Level Analyzers (HLAs)
    • Measurement Extensions
      • Analog Measurement Extensions
      • Digital Measurement Extensions
    • Extension File Format
    • About Third-Party Extensions
    • Disabling Marketplace Extensions
    • Publish an Extension
    • HLA - Analyzer Frame Format
      • Async Serial - Frame Format
      • I2C - Frame Format
      • SPI - Frame Format
      • CAN - Frame Format
      • Manchester - Frame Format
      • 1-Wire - Frame Format
      • Async RGB LED - Frame Format
      • Simple Parallel - Frame Format
      • LIN - Frame Format
      • I2S - Frame Format
    • API Documentation
  • Automation & Analyzer SDK
    • Automation API - Logic 2
    • Automation API - Legacy Logic 1.x
    • Protocol Analyzer SDK
      • FrameV2 / HLA Support - Analyzer SDK
      • Rename a Custom Analyzer
    • More Information on our SDKs
      • Can I Access Raw Data in Real Time?
      • Migrate Code to the New Analyzer SDK
      • Sharing Custom Low-Level Analyzer (LLA) Code
      • VB.NET Support for Automation
  • Datasheets & Specifications
    • Datasheets
    • Logic Hardware Revisions
    • Logic Dimensions
    • Compliance Documents
  • Troubleshooting
    • Installation Errors
    • The Software Fails to Launch
    • The Software Crashes
    • Logic is Not Detected
    • Getting your Machine ID
    • Getting your Software Crash Logs
    • Getting the Console Output
    • Location of Your Config File
    • Error Message: ReadTimeout
    • The Captured Data Looks Incorrect
    • The Captured Data is Corrupted
    • A Protocol Analyzer Produces Unexpected Results
    • The 'Waiting for Trigger' Window Never Closes
    • Device USB VID and PID Information
    • Error Message: Out of Memory Exception Was Thrown
    • PC Performance Issues with Logic
    • Data Export Is Not Working
    • Error Message: A device was found, but the software was unable to access it
    • Trouble Downloading the Latest Software
    • Logic Does Not Connect over USB 3.0
    • Why Am I Seeing Spikes in the Digital Capture?
    • Logic Interferes with My Circuit Operation
    • The Add Analyzer Menu Is Not Displaying
    • Other Drivers Interfere with Logic's Operation
    • The Maximum Sample Rate is Not Selectable
    • The Digital and Analog Recording on the Same Channel Appear Different
    • Advanced USB Debugging for USB 3.0 Users with Linux Kernels 3.3 and Older
    • Saving or Loading Anything Crashes the Software
    • Error Message: The application was unable to start correctly (0xc0000005)
    • Memory Usage with Triggered Captures
    • The Cabinet File disk1.cab has an Invalid Digital Signature (Logic 1.x)
    • Software Crashes with Virtual Desktops
    • Pre-Trigger Buffer is Incomplete
    • Linux Shared Memory Crash
    • Missing Files: api-ms-win-crt-runtime-l1-1-0.dll or msvcp140.dll
    • Known Issues on OS X
    • A Measurement Appears Incorrect
    • All Known Issues
    • USB 3.0 Cable Customer Notice (2017)
    • Warning Message: Logic Pro is running as a USB 2.0 device
    • Software Issues with Encryption Products
    • Linux Permission Requirements for Logic Software
    • My Rise Time and Fall Time Measurements Seem Incorrect
    • The Analog Waveform Loads Very Slowly after Capture Is Complete
    • Input Channels are Missing
    • Exported MATLAB File Does Not Open
    • Saleae Logic LED Blinks Red
    • Crashes Caused by macOS Mojave (10.14)
    • Troubleshooting Signal Crosstalk
    • Error Message: DeviceSetupFailure
    • Error Message: Unable to detect WebGL and Other GPU Issues
    • Warning Message: Unsupported Version
    • Error Function: Device2::SetupDevice
    • Warning Message: Possible USB Host Controller Problem Detected
    • Error Message: StartCommandError
    • Logic 2 Error Messages
    • PC Detection Test
    • CentOS Compatibility Issues
    • Error Message: Failed to Load Extension
    • CSV Export is Slow
    • Set an Analyzer Starting Point in your Capture
    • Logic 2 is Consuming Disk Space
    • Connection Conflicts with USB Debuggers
    • PC Restart Causes Logic to Disconnect
    • HLA Fails to Display Special Characters
    • Data Table Shows Incorrect Values
    • Error Message: Failed to Load Custom Analyzer
    • Error Message: Capture Stopped
    • Error Loading Marketplace Extensions
    • Error: Capture stopped because backlog data exceeded 90%
    • This Analyzer's Native Export is Not Supported in Logic 2
    • Mouse Scrolling Issues
    • Error: A device was found, but it was removed before initialization completed
    • Error: An unknown error occurred during device connection
    • Visual Studio Error: Failed to Launch Debug Adapter
    • VS Code Fails to Launch Python Automation API Script
    • Analog Waveforms Do Not Appear on Linux
    • Reinstall USB Host Controller Drivers
  • FAQ
    • Technical FAQ
      • System Requirements for Saleae Products
      • What Is the Normal Behavior of the LED?
      • What Is the Difference between Logic/Logic16 (Gen1) and Logic 8/Pro 8/Pro 16 (Gen2)?
      • Recommended USB 3.0 Host Controller Cards
      • Device Settings Configuration Tips
      • What Is the Worst Case Channel to Channel Skew?
      • What is Asynchronous Sampling?
      • Which Saleae Products Can Decode 4-Bit Parallel LCD Communications?
      • How Can I Compare Two Clock Signals for Synchronization and Drift?
      • Converting I2S/PCM Captures into Audio
      • My Capture Shows an Uneven Duty Cycle
      • Can I Create or Edit .logicdata Files?
      • Can Saleae Logic Run on ARM / Apple Processors?
      • What Annotations Are Supported?
      • Time & Memory Saving Tools
      • How Can I Record Power Consumption?
      • Moving Logic to Its Own Host Controller
      • How Long Does It Take to Save a File?
      • XMonad on Linux Causes Issues
      • What Is the Maximum Bandwidth of Logic?
      • How Long Can I Record Data?
      • Can I Export Protocol Results Between Timing Markers?
      • Can I Generate an Analog Graph from Digital Data?
      • Time Measurement Error
      • Can These Products Replace an Oscilloscope?
      • Can I Use Multiple Logics on a Single PC?
      • Native Windowing Features Are Not Working Such as Snap or Gestures
      • Opening .logicdata Capture Files
      • How to Choose the Right Logic Analyzer for You
      • Saleae Open Source Support
      • How to Trigger the End of a Capture Instead of the Start
      • Using the Hardware with USB Extension Cables, Through Virtual Machines, or Ethernet Extenders
      • Are the Ground Pins Required for Each Input Used?
      • Can Saleae Products Output Data?
      • Resolution of the Analog Inputs
      • What Sampling Rate Should I Use?
      • Can I Share Data Captures with Others?
      • Binary Export Format (Digital) - Logic 1.x
      • MATLAB Data Export Format - Legacy Logic 1.x
      • Recording Multiple Protocols at the Same Time
      • Changing the Display Radix (Base)
      • Which Logic Analyzer Should I Get?
      • How to View and Debug Firmware Variables, State, and Function Calls
      • Using Saleae Logic Devices with Third-Party Pattern Generators
      • Can Logic Operate with a Full-Speed USB Isolator?
      • Which Saleae Devices Support Analog Recording?
      • How to Manage Protocol Analyzers when Using the Socket API
      • How to Export Serial Protocol Results to a Raw Binary File
      • How to Trigger On a Pulse with No Maximum Time Limit - Logic 1.x
      • Finding Your USB 3.0 Host Controller Information
      • Logic Reports Different USB Current Requirements
      • Is It Possible to Adjust the Logic Thresholds for the Digital Inputs?
      • Why Does Channel 0 Use a Black Wire?
      • Software Shows Multiple Logic Analyzers Attached
      • Are the Input Channels Isolated from Each Other?
      • Are There Feature Differences in the Software when Different Logic Analyzers Are Used?
      • Packet Level Decoding Support in the Analyzer SDK
      • What Higher-Level Protocol Analysis Features Are Available?
      • Support for USB 3.0 and USB 3.1
      • How Can I Compare Signals from Different Captures?
      • Do the Saleae Logic Analyzers Support Trigger Out?
      • Why is the Length of my Capture Incorrect?
      • The Options Button is Missing
      • Can I Change the Voltage Range of the Analog Inputs?
      • How Does the ASCII Radix Display Characters?
      • Do I Have a USB 3.0 Port?
      • What Is the Best Way to Compare Similar Sequences of Protocol Data?
      • Which Version of the Software Should I Use?
      • Import Custom Low Level Analyzer
      • OSX Analyzer SDK Xcode Setup
      • Can Custom Analyzers Process Analog Channels?
      • Automating Long Overnight Captures
      • What Options Are There to Export Multiple Protocol Analyzer Results into the Same File?
      • Do the Saleae Devices Support AC Coupling?
      • Suggestions for Capturing Multiple Instances of a Triggered Event Automatically
      • How Many Protocol Analyzers Can Be Used at Once?
      • Is It Possible to Run the Saleae Software on a PC without SSE2 Instructions?
      • Is It Possible to Import Data into the Logic Software?
      • How Do I Convert Exported CSV Analog Data in Voltages?
      • Is There Cross-Platform Support for the SaleaeSocketApi C# Project
      • Why Does Logic Get Warm?
      • Binary Export Format (Analog) - Logic 1.x
      • Electrical Isolation Suggestions
      • FCC and CE Testing Recommendations
      • 'Save Capture' and 'Export Data' is Disabled in the Software
      • File Format Description for Exporting Protocol Analyzer Results
      • Is There a Newer Version of the Software Available?
      • Is There a Way to Change the Window Resolution?
      • How Can I Extract Recorded Data Using Socket API?
      • Does the Software Support Windows 10 Tablets or Windows RT Tablets?
      • Standalone Software Information
      • Does the Saleae Software Support the Original Logic and Logic 16?
      • Timing Markers Disappear When I Start a New Capture
      • What Sample Rate Settings Are Available? Can I Sample at a Slower Rate?
      • How Do I Differentiate Data in the Export File when Duplicate Analyzers Are Used?
      • Running Multiple Versions of the Software
      • Test Clip Differences - Gen 1 & Gen 2
      • USB-C Cable Recommendations
      • Is My Capture Data Private?
      • Ethernet Connectivity Suggestions
      • Binary Export Format - Logic 2
      • Viewing I2C Addresses as 8-bit
      • Can I use Python Packages in my Custom Extension?
      • Are the Inputs Synchronously Sampled or Sweep Sampled?
      • Is Logic Affected by the Log4j Exploit?
      • Connecting Remotely with SSH
      • Is Silent Installation Supported?
      • Is the .sal File Format Documented?
      • Export Data via Socket API
      • Running Logic in a CI Environment on Windows with the SYSTEM Account
    • General FAQ
      • How Do I Get More Help on an Issue That's Outside the Scope of Saleae Support?
      • How to Identify Each Saleae Device
      • License for the Saleae Logic Software, SDKs, and APIs
      • How Do You Pronounce Saleae?
      • How to Create Project Content for Saleae
  • Returns & Warranty
    • Submit a Warranty Claim
  • Community
    • Ideas & Feedback
    • User Forum
    • Community Projects
    • Community Created Accessories
    • Community Shared Analyzers
  • Tutorials
    • Oscilloscope Tutorial
    • Logic Analyzer Tutorial
    • Learning Portal
      • Digital Protocols
        • Learn Asynchronous Serial
        • Learn I2C - Inter-Integrated Circuit
        • Learn SPI - Serial Peripheral Interface
        • Learn CAN – Controller Area Network
        • Digital MultipleX (DMX512)
        • Manchester
        • 1-Wire
        • Learn I2S / PCM
        • Management Data Input/Output (MDIO)
        • BiSS C
        • HDMI Consumer Electronics Control (CEC)
        • PS/2 Keyboard/Mouse
        • Universal Serial Bus (USB) 2.0
        • Single-Wire Interface (SWI)
        • Simple Parallel
        • Local Interconnect Network (LIN)
        • Joint Test Action Group (JTAG)
      • Common Acronyms and Definitions
      • What is a Glitch?
      • What is RAM? Why Does Logic Use it?
      • What is a Display Radix?
      • What is Data Bandwidth? Can I Reduce this in Logic?
    • Example Projects
      • STM32 Nucleo Board - Digital Signals
      • STM32 Nucleo Board - Analog Signals
      • STM32 Nucleo Board - Analyzing UART
      • STM32 Nucleo Board - Analyzing SPI
      • STM32 Nucleo Board - Analyzing I2C
Powered by GitBook
On this page
  • Learn SPI - Serial Peripheral Interface
  • SPI and Synchronous Serial
  • Serial vs. Parallel
  • Synchronous Serial vs. Asynchronous Serial
  • How the Clock Line Tells Us When to Read the Data Line
  • Rising Edge or Falling Edge?
  • Synchronization – Which Bit Belongs to Which Byte?
  • Enable and Disable
  • A Simple Implementation of Synchronous Serial – the Shift Register
  • Point-to-Point Connection
  • Bus
  • The SPI Way
  • Only One Master
  • The Lowly Slaves
  • Choosing Which Slave Gets to Talk with the Master
  • SS or EN
  • Enable (EN or SS) Is Active Low
  • Communications with the Active Slave
  • Further Reading
Edit on GitHub
Export as PDF
  1. Tutorials
  2. Learning Portal
  3. Digital Protocols

Learn SPI - Serial Peripheral Interface

PreviousLearn I2C - Inter-Integrated CircuitNextLearn CAN – Controller Area Network

Last updated 6 years ago

Learn SPI - Serial Peripheral Interface

SPI (serial peripheral interface) is a common application of synchronous serial—where a dedicated clock line indicates when to read one or more data lines. Generally, SPI consists of a single master (typically a microcontroller) and one or more slave devices. In a typical application, there are 4 wires: A clock line, an enable line, a dedicated master-to-slave data line, and a dedicated slave-to-master data line.

SPI and Synchronous Serial

SPI is a particular type of synchronous serial. We'll start by discussing the characteristics of synchronous serial.

Serial vs. Parallel

Serial (as opposed to parallel) means one bit (1 or 0) is placed on the bus (wire or wires) at a time.

Synchronous Serial vs. Asynchronous Serial

When we talked about asynchronous serial, recall that the receiver was responsible for figuring out exactly when a bit should be read from the bus. To do this, we used a timer and kept track of how much time had elapsed. At certain time intervals, we would record what was on the bus.

With synchronous serial, things are more straightforward. We are explicitly told when we should read the data line. To do this, another wire is added (for a total of 2 wires). This other wire, called the clock line, tells us when to read the data line.

How the Clock Line Tells Us When to Read the Data Line

There are several ways in which the clock line could tell us when to read the data line. For example, maybe we should read the data line whenever the clock line is a logic 1. A better way is to use the "edge" or "transition" between logic states to indicate that the data line should be read. This has the advantage of being a single event—a single snapshot in time—rather than a region of time. This reduces any ambiguity about when exactly the data line should be read.

Rising Edge or Falling Edge?

Synchronization – Which Bit Belongs to Which Byte?

We know when to read a bit, but how do we know which bit we are reading? In other words, how do we synchronize? The most straightforward way to synchronize is to use a third wire. Ahead of time, we decide that a rising (or falling) edge of that wire will be our synchronization event. Typically, this wire is called enable or reset (but it's the same idea.) It allows the different parts of a system to synchronize—to revert to a known starting state.

Enable and Disable

The enable line is used for synchronization, but it usually also serves another purpose. Its state (0 or 1) indicates if something should be enabled or disabled. For example, maybe you don't need a particular device to be running all the time. You may be able to disable it, putting it into a low power mode. In SPI, that has the added benefit of choosing which device you want to talk to. You simply disable all the devices except the one you want to talk to.

A Simple Implementation of Synchronous Serial – the Shift Register

In practice, shift registers are often used in the implementation of SPI.

Point-to-Point Connection

There are many possible ways in which a synchronous serial could be used with more than two devices. One simple way is that each pair of devices that needs to communicate has dedicated connections. Notice, however, that the number of connections you need grows geometrically. So this isn't a great solution.

Bus

A bus is a collection of wires shared by many devices.

Notice that a bus uses far fewer connections. However, there are some limitations:

  • Only one device can "talk" at a time.

  • If two devices talk at a time, this is a "bus collision." Imagine what happens if one device outputs a 0 at the same time another device outputs a 1. That is a short circuit!

  • A device needs some way of knowing if someone is already talking on the bus.

  • The bus needs to recover from potential conflicts and have a way to figure out who gets to go first.

While a bus topology like the one shown is very powerful, it requires electrical- and protocol-level complexity to deal with the issues raised above. It's not ideal for very cheap and simple devices.

The SPI Way

SPI uses a bus but makes a few compromises to make things very simple.

Only One Master

In SPI, only one of the devices is in charge. It alone decides who can talk on the bus. Furthermore, devices can only talk to the master device; they can't talk to each other.

The Lowly Slaves

All other devices on the SPI are called slaves.

Choosing Which Slave Gets to Talk with the Master

In SPI, the master uses an enable line for each and every slave. In this way, the master can select which slave is active. Generally speaking, only one slave can be active at a time.

SS or EN

In SPI, the enable line is usually called SS (slave select) or EN (enable). It's all the same thing.

Enable (EN or SS) Is Active Low

The SPI enable line is almost always inverted: 1 means disabled; 0 means enabled.

Communications with the Active Slave

MOSI

In SPI, the master has a dedicated data output line called MOSI (master out, slave in). All the slaves listen on this line but ignore it if they are not active. In SPI, data are typically sent most significant bit first (MSB first).

MISO

The master also has a dedicated data input line called MISO (master in, slave out). Only the active slave is allowed to transmit on this line. All the other slaves MUST transition to high-z mode when they are not active (i.e., they may not drive the line). This is the function of a tri-state buffer. In SPI, data are typically sent most significant bit first (MSB first).

CLK

Since this is synchronous serial, there needs to be a clock, which is typically called CLK. The clock is used with both the MOSI and MISO data lines.

The Unspecified Details

SPI leaves a couple things unspecified. For example, should a slave read the MOSI line on CLK's rising edge or its falling edge? An additional complication is that the slave must generate output data on MOSI such that its data will be valid when the master reads it in accordance with its own CLK signal. That is a little backward.

Clock Polarity and Phase – CPOL and CPHA

Datasheets specify the previously mentioned details in terms of clock polarity (CPOL) and clock phase (CPHA). An additional complication is that the slave must generate output data on MOSI such that its data will be valid when the master reads it in accordance with its own CLK signal. That is a little backward. Clock polarity (CPOL) is the state of the clock at the moment a slave's enable line becomes active. CPOL=0 means that the clock is low (0) as the slave becomes enabled. CPOL=1 means the clock is high (1) when the slave becomes enabled.

At some point after a slave becomes active, the clock likely will change. If the data on MOSI and MISO should be read on this first edge, the Clock Phase (CPHA) is 0. Alternatively, if data on MOSI and MISO should be read the 2nd time the CLK changes, the Clock Phase (CPHA) is 1. CPOL=0 (the clock starts out low) CPHA=0 (data is valid on the 1st clock edge)

CPOL=0 (the clock starts out low) CPHA=1 (data is valid on the 2nd clock edge)

CPOL=1 (the clock starts out high) CPHA=0 (data is valid on the 1st clock edge)

CPOL=1 (the clock starts out high) CPHA=1 (data is valid on the 2nd clock edge)

SPI Variations / Settings

Clock Polarity and Clock Phase

The SPI variations you'll typically need to worry the most about is the clock polarity and clock phase discussed above.

Bit Rate

The bit rate is the fastest speed at which the CLK line will operate. This can vary wildly with the application, from a few hundred bits per second to many tens of MHz. Since the CLK line provides us when to read the data line, there is no significant difference in how things operate, assuming all the devices can keep up.

Bit Order

Data are sent over the SPI most significant bit first. However, you may find yourself using SPI code or an SPI hardware peripheral with synchronous serial that isn't strictly SPI.

Bits per Transfer/Word

In most applications, data sent over an SPI are byte-oriented. However, there is no fast rule in this area, so technically, any number of bits could comprise a word. SPI synchronizes using the Enable (or SS) line; there is no delimiter to specify when one word ends and the next begins.

Enable/Slave Select Polarity

SPI applications typically use logic 0 as the active state for the enable line. For synchronous serial more generally, this could easily be the other way around.

Some Good Resources

Example Parts That Use SPI

Further Reading

Top Resources

Example SPI Parts

What Logic Decodes

  • Four main modes of SPI

  • CPOL (both modes)

  • CPHA (both modes)

  • MSB first or LSB first

  • MISO and MOSI data

  • With our without enable line

The rising edge (also called positive edge or posedge) is when the state changes from a low to a high (0 to 1). The falling edge (also called negative edge or negedge) is when the state changes from a high to a low (1 to 0). In SPI, data are only ever valid (should be read) on either the rising or falling edge. Which one it is—rising or falling edge—depends on the implementation. For existing parts and systems, you'll have to look it up (typically in a datasheet). In some applications, you may have the flexibility to use either (you'll need to pick one), and then make sure everyone sticks to the standard.

Wikipedia
Microchip SPI Presentation
EEPROM
LCD
Magnometer
SD Card
Gyro
Analog to Digital Converter (ADC)
Pressure Sensor
Wikipedia
Microchip SPI Presentation
EE Times SPI Article
EEPROM
LCD
Magnometer
SD Card
Gyro
Accelerometer
Analog to Digital Converter (ADC)
Pressure Sensor