The Saleae Logic software includes the following protocol analyzers:
- Asynchronous Serial
- Atmel SWI (Single Wire Interface)
- CAN (Controller Area Network)
- HD44780 Parallel LCD
- HDLC (High-Level Data Link Control)
- I2S Audio / PCM
- I3C (see section below)
- LIN (Local Interconnect Network)
- MDIO (Management Data Input/Output)
- Manchester (Differential, Bi-Phase Space, and Bi-Phase Mark)
- Modbus RTU & ASCII
- PS2 Keyboard & Mouse
- SMBus (includes PMBus and Smart Battery)
- SPI (Serial Peripheral Interface)
- SWD (ARM Serial Wire Debug)
- Synchronous Parallel
- USB Low Speed and Full Speed
We plan on officially bringing I3C protocol support to Saleae Logic, and we currently have a working solution! If you're interested in more details, please contact us.
I3C Analyzer running on Logic 2
The I3C analyzer will be released as our first "premium" analyzer, meaning that it will require a paid license to use it within our software (we're currently working out the details behind how this might work). We believe that we can provide an amazing developer experience at a price point that is a great deal for customers who are already using new protocols, and at the same time, helps us generate enough revenue to continue working on new features. We welcome any and all feedback!
We provide user guides for a handful of our protocol analyzers, which we have listed in the link below.
Some Logic users have created their own protocol analyzers. The following list of analyzers are available but not officially supported by Saleae.
Yes. However, you will need to use a device with sufficient bandwidth to record the original signal. For instance, Logic 4 simply does not have the bandwidth required to capture and decode USB full speed. Logic 4 has a maximum digital bandwidth of 3 MHz, and USB full speed requires a digital bandwidth of at least 12.5 MHz.
Unfortunately, we have not yet ported the UNI/O analyzer from Logic v1 into the newer Logic v2 software. Specifically, it requires separate API functions that we simply haven't had the chance to implement yet. It's not on the roadmap at the moment, though we would like to gauge user interest in this before we commit to it, as porting this analyzer into Logic v2 would require quite a bit of work as compared to porting our other analyzers.