After that filter, the input is connected to a digital comparator, which is also fed with a selectable reference voltage. In the case of Logic 8 or Logic 4, a digital buffer chip is used. That signal is finally passed into the FPGA where it is sampled at the internal sample rate of the device (500 MSPS for Pro devices, 100 MSPS for Logic 8). In the case of Logic 4, no FPGA is used, and the data is sampled using the latch feature of the digital buffer IC.