The Saleae Logic software includes a protocol decoder to read clocked (synchronous) parallel bus data. The analyzer supports between 1 and 16 bits of data bus, although realistically, only 15 bits are possible.
Keep in mind that this isn't the "state" mode you may have seen in other logic analyzers. All Saleae units operate by over-sampling only and do not support a state/external clock mode. That means you will need to sample at least 4 times faster than the parallel clock frequency.
To use the parallel analyzer, first make sure you record all of the data signals and the clock signal in one capture. The exact ordering of the inputs relative to the parallel bus does not matter.
Once you have captured your data, add the simple parallel analyzer using the "+" button on the analyzer panel.
The settings for the parallel analyzer are very important. First, for all unused data bits, change the selected channel to "None". For instance, if you're using a 4-bit data bus, change D4-D15 to "None" in the settings as shown below.
Then, correctly assign the data bits you are using to the corresponding channels.
Finally, set the clock channel and the clock edge correctly and press Save.
Decoding the Parallel Data
Click on the gear icon next to the "Simple Parallel" analyzer and select the preferred numeric format. The image below shows an example of decoding a 4-bit data bus into the hexadecimal format.
Export File Format
The protocol export will create a file using the currently selected display radix (hex demonstrated here). The export format has a header row and then 1 row per recorded parallel value. The values are the same as displayed in the displayed frames over the clock channel. There is one row per valid clock edge, either rising or falling, as specified in the analyzer settings.
Here is a sample of a file: