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Simple Parallel

Brief description:

Generally speaking, a parallel bus has multiple data lines and a single clock line. Data is valid - and is sampled - on a specified edge (typically rising or falling) of the clock line.

Top resources:
Example Simple Parallel Parts:
What Logic decodes:

  • Rising edge or falling edge of clock
  • One to eight data lines

trello ID: 572919331a98d7676836ac2a
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