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Simple Parallel

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Brief Description

Generally speaking, a parallel bus has multiple data lines and a single clock line. Data is valid—and sampled—on a specified edge (typically rising or falling) of the clock line.


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Example Simple Parallel Parts
What Logic Decodes

  • Rising edge or falling edge of clock
  • One to eight data lines

trello ID: 572919331a98d7676836ac2a

trello data: 1702448848
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