The Saleae Logic software includes a protocol decoder to read clocked (synchronous) parallel bus data. The analyzer supports between 1 and 16 bits of data bus, although realistically, only 15 bits are possible.
Keep in mind that this isn't the "state" mode you may have seen in other logic analyzers. All Saleae units operate by over-sampling only, and do not support a state/external clock mode. This means you will need to sample at least 4 times faster than the parallel clock frequency.
To use the parallel analyzer, first make sure you record all of the data signals and the clock signal in one capture. The exact ordering of the inputs relative to the parallel bus does not matter.
Once you have captured your data, add the simple parallel analyzer using the "+" button on the analyzers panel.
The settings for the parallel analyzer are very important. First, for all unused data bits, change the selected channel to "None". For instance, if you're using a 4 bit data bus, change D4-D15 to "None" in the settings.
Then, correctly assign the data bits you are using to the corresponding channels.
Finally, set the clock channel and the clock edge correctly and press save.
For more information about exporting protocol analyzers and analyzer display base (hex, ascii, etc) see this section of the user manual: Using Protocol Analyzers.
Export File Format
The protocol export will create a file using the currently selected display radix (hex demonstrated here). The export format has a header row, and then 1 row per recorded parallel value. The values are the same as displayed in the displayed frames over the clock channel. There is one row per valid clock edge - either rising or falling, as specified in the analyzer settings.
Here is a sample of a file:
Time [s],Value 0.000020000000000,0x0000 0.000040000000000,0x0001 0.000060000000000,0x0002 0.000080000000000,0x0003 0.000100000000000,0x0004 0.000120000000000,0x0005 0.000140000000000,0x0006
Older versions of the software would not decode the last valid clock edge if there were no more transitions on the clock channel. For instance, if data was valid on the rising edge of the clock, then the analyzer would ignore that last rising edge if it was not followed by a falling edge, and the clock channel just held the state for the rest of the capture. This issue is fixed in the latest beta software, which can be downloaded here: Saleae Logic Beta Software.
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